GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 91

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

9.3.3.2
9.3.3.3
Datasheet
Table 24. Modem Function Event Mask Register
Table 25. Modem Function Present State Register
Modem Function Event Mask Register
The Modem Function Event Mask register masks CSTSCHG and INTA# assertion as shown in
Table 24
Modem Function Present State Register
The Modem Function Present State register specifies the current state of an event’s sources as
shown in
31:16
15
14
13:7
6:5
4
3
2
1
0
31:16
15
14:5
4
3
Bits
Bits
below.
Reserved
INTR
WKUP
Reserved
PWM
BAM
GWAKE
Reserved
BVD RDY
BVD WP
Reserved
Reserved
INTR
Reserved
GWAKE
Reserved
Table 25
Function
Function
below.
0
0b
0b
0
0
0b
0b
0b
0b
0b
0
0
0
0
0b
Default
Default
Bits [31:16] are reserved in the CardBus Specification.
This bit is the interrupt mask. When this bit equals 0b, it masks the
modem function INTA# line but has no effect on the Modem Function
Event register. The modem function can assert the INTA# signal only
when both fields are enabled: the interrupt bit and the modem control
bit in the System Control Block (SCB) register within the CSR space.
The interrupt mask bit affects the INTA# masking only after the OS has
set this register. Thus, on legacy systems that do not access the status
change registers, the modem INTA# signal is not masked by the
interrupt.
This bit is the wake-up mask. When this bit equals 0b, it masks the
modem function CSTSCHG signal but has no effect on the Function
Event register. This bit is dependent on bit 4 of this register.
Bits [13:7] are reserved in the CardBus Specification.
These bits are used for Pulse Width Modulation Binary Audio Enable.
(PWM BAM).
This bit is the general wake-up mask. When this bit equals 0b, it masks
the modem function wake-up events towards the CSTSCHG signal. It
has no effect on the Modem Function Event register. The 82559 can
assert the CSTSCHG signal in the following configuration of masked
bits: wake-up bit AND general wake-up bit, or PME Enable bit in the
PMCSR register only.
Bit 3 is reserved in the CardBus Specification.
Bit 2 is used as the Battery Voltage Detect Ready (BVD RDY) bit.
Bit 1 is used as the BVD Write Protect (WP) bit.
Bit 0 is reserved in the CardBus Specification.
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for interrupts. It reflects the current state of the Modem
Interrupt (MINT) input pin from the modem.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. It reflects the current inverse state
of the Modem Ring (MRING#) input pin from the modem.
Bit 3 is reserved in the CardBus Specification.
Description
Description
Networking Silicon — 82559
83