GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 80

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
72
MDI Control Register:
Receive DMA Byte Count:
Flow Control Register:
PMDR:
General Control:
General Status:
Function Event:
Function Event Mask:
Function Present State:
Force Event:
The MDI Control register allows the CPU to read and write
information from the PHY unit (or an external PHY component)
through the Management Data Interface.
The Receive DMA Byte Count register keeps track of how many
bytes of receive data have been passed into host memory via DMA.
This register holds the flow control threshold value and indicates
the flow control commands to the 82559.
The Power Management Driver Register provides an indication in
memory and I/O space that a wake-up interrupt has occurred. The
PMDR is described in further detail in
Management Driver Register” on page
The General Control register allows the 82559 to enter the deep
power-down state and provides the ability to disable the Clockrun
functionality. The General Control register is described in further
detail in
The General Status register describes the status of the 82559’s
duplex mode, speed, and link. The General Status register is
detailed in
The Function Event Register is used for CardBus power
management applications and specifies the event that changed the
status. The Function Event register is further defined in
9.1.14.1, “LAN Function Event Register” on page
The Function Event Mask register masks the CSTSCHG signal
assertion for specified events. The Function Event Mask register is
further defined in
Register” on page
The Function Present State register reflects the current state of each
condition that may cause a status change or interrupt. The Function
Present State register is further defined in
Function Present State Register” on page
The Force Event register simulates the status change events for
troubleshooting purposes. The Force Event register is further
defined in
page
79.
Section 9.1.12, “General Control Register” on page
Section 9.1.14.4, “LAN Force Event Register” on
Section 9.1.13, “General Status Register” on page
Section 9.1.14.2, “LAN Function Event Mask
77.
Section 9.1.11, “Power
75.
78.
Section 9.1.14.3, “LAN
77.
Datasheet
Section
76.
76.