GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 35

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

4.3.1.2
4.3.1.3
4.3.1.4
Datasheet
1. For a topology of two 82559 devices connected by a crossed twisted-pair Ethernet cable, the deep power-down mode should be disabled. If
it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes
become active.
D0u is the 82559’s initial power state following a power on reset event and prior to the Base
Address Registers (BARs) being accessed. While in the D0u state, the 82559 has PCI slave
functionality to support its initialization by the host and supports Wake on LAN* mode.
Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration space
switches the 82559 from the D0u state to the D0a state.
In the D0a state, the 82559 provides its full functionality and consumes its nominal power. In
addition, the 82559 supports wake on link status change (see
page
frequency greater than 16 MHz) for proper operation. During idle time, the 82559 supports a PCI
clock signal suspension using the Clockrun signal mechanism. The 82559 supports a dynamic
standby mode. In this mode, the 82559 is able to save almost as much power as it does in the static
power-down states. The transition to or from standby is done dynamically by the 82559 and is
transparent to the software.
D1 Power State
In order for a device to meet the D1 power state requirements, as specified in the Advanced
Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus
transmission or interrupts; however, bus reception is allowed. Therefore, device context may be lost
and the 82559 does not initiate any PCI activity. In this state, the 82559 responds only to PCI
accesses to its configuration space and system wake-up events.
The 82559 retains link integrity and monitors the link for any wake-up events such as wake-up
packets or link status change. Following a wake-up event, the 82559 asserts the PME# signal to
alert the PCI based system or the CSTSCHG signal for a CardBus system.
D2 Power State
The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2
state, the 82559 will consume less current than it does in the D1 state. In addition to D1
functionality, the 82559 can provide a lower power mode with wake-on-link status change
capability. The 82559 may enter this mode if the link is down while the 82559 is in the D2 state. In
this state, the 82559 monitors the link for a transition from an invalid link to a valid link. The 82559
will not attempt to keep the link alive by transmitting idle symbols or link integrity pulses.
sub-10 mA state due to an invalid link can be enabled or disabled by a configuration bit in the
Power Management Driver Register (PMDR).
D3 Power State
In the D3 power state, the 82559 has the same capabilities and consumes the same amount of power
as it does in the D2 state. However, it enables the PCI system to be in the B3 state. If the PCI
system is in the B3 state (in other words, no PCI power is present), the 82559 provides wake-up
capabilities if it is connected to an auxiliary power source in the system. If PME is disabled, the
82559 does not provide wake-up capability or maintain link integrity. In this mode the 82559
consumes its minimal power.
The 82559 enables a system to be in a sub-5 watt state (low power state) and still be virtually
connected. More specifically, the 82559 supports full wake-up capabilities while it is in the D3
state. The 82559 can be connected to an auxiliary power source (V
31). While it is active, the 82559 requires a nominal PCI clock signal (in other words, a clock
Section 4.3.2, “Wake-up Events” on
AUX
Networking Silicon — 82559
), which enables it to provide
1
The
cold
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