CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 65

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 2-1. Hardware Signal Definitions (3 of 6)
28236-DSH-001-B
TxClav
TxEn*
TxClk
RxAddr[4:0]
RxData[15:0]
RxPar
RxSOC
RxClav
RxEn*
RxClk
Pin Label
Transmit Flag
Transmit Enable
Transmit Clock
Receive Address
Receive Data
Receive Data Parity
Receive Cell Marker
Receive Flag
Receive Enable
Framer Control/Clock
Signal Name
Mindspeed Technologies
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
In UTOPIA mode, TxClav indicates that the transmit buffer in
the downstream link interface chip is full and no more data
can be accepted. In slave UTOPIA mode, this pin indicates to
the link interface chip that the CN8236 transmit buffer is
empty. (Has pulldown resistor to pull inactive in master mode
when not driven externally.) (aka TxFlag*) (8 mA drive)
Indicates that valid data has been placed on the TxData[15:0],
TxPar, and TxSOC lines in the current clock cycle when the
CN8236 is in UTOPIA or slave UTOPIA mode. This pin is an
output in UTOPIA mode and an input in slave UTOPIA mode.
(8 mA drive. Has pullup resistor to pull inactive in slave mode
when not driven externally.)
UTOPIA Transmit Clock. Has an internal pullup to V
level).
UTOPIA receive address (8 mA drive).
Transfers incoming data bytes from the link interface or
framer chip to the CN8236 in all framer modes.
Should be driven with the 8-bit odd parity computed over the
RxData[7:0] lines by the link interface or framer chip in all
framer modes.
Indicates that the current byte being transferred on the
RxData[7:0] lines is the starting byte of a 53-byte cell. Has
internal pulldown resistor. (aka RxMark)
In UTOPIA mode, RxClav indicates that the receive buffer in
the downstream link interface chip is empty, no more data can
be transferred, and the RxData[7:0], RxPar, and RxSOC lines
are invalid. In slave UTOPIA mode, this pin indicates to the
framer chip that the receive FIFO buffer in the CN8236 is full.
8 mA drive. Has pulldown resistor to pull inactive in master
mode when not driven externally. (aka RxFlag*)
In UTOPIA mode, RXEN* indicates that the CN8236 is ready
to receive data on the RxData[15:0],RxPar, and RxSOC lines in
the next clock cycle. This pin is an output in UTOPIA mode
and an input in slave UTOPIA mode. Has pullup resistor to pull
inactive in slave mode when not driven externally. 8 mA drive.
In UTOPIA and slave UTOPIA mode, the RxCLK line should be
driven with a clock that is synchronous to that used by the
framer device for interfacing to the CN8236. The
TxData[15:0], TxPar, TxSOC, TxClav, TxEn*,
RxData[15:0],RxPar, RxSOC, RxClav, and RxEn* lines must be
synchronous to this clock in UTOPIA mode, and maintain the
specified setup and hold times with reference to its rising
edge. When MULTI_CLK is set to a 1 in the CONFIG1 register,
the Tx side of the UTOPIA interface is synchronized to the
TxClk.
™
2.10 Logic Diagram and Pin Descriptions
Definition
2.0 Architecture Overview
DD
(CMOS
2-31