CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 281

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
28236-DSH-001-B
11.2 Unimplemented PCI Bus Interface
Functions
The PCI bus interface on the CN8236 does not implement all transaction types
defined by the PCI bus specification; only those sections of the protocol that are
necessary for slave and DMA memory accesses are implemented. In particular,
the following transaction types are not implemented:
Specification. Assume that a logic low on the HSWITCH* input is switch locked
and a logic high is switch unlocked.
NOTE:
• 64-bit transfers, and the Dual Address Cycle command.
• Snooping and cache support. Memory Read Line, Memory Write, and
• Locked and exclusive accesses: the PCI LOCK* line is not driven by the
• I/O accesses (the I/O Read and I/O Write commands).
• Interrupt acknowledge cycles, including the Interrupt Acknowledge
• The Special Cycle command and Special Cycle transactions.
• Burst transfers that do not have simple, sequentially incrementing
Implement Sections 3.1.8 and Section 7.2 of Compact PCI Hot Swap
Invalidate commands are internally aliased to the Memory Read and
Memory Write commands as per the PCI specification.
CN8236, and the PCI slave interface does not handle locked accesses by
other bus masters in any special manner.
command.
addresses for consecutive data phases. The PCI master logic always
performs sequentially incrementing burst transfers. The two LSBs of the
PCI address lines (AD[1,0]) must be 0 during the address phase of any
transfer made to the PCI slave logic (indicating sequentially incrementing
burst addresses). If AD[1,0] is not equal to 0, the slave logic signals a type
A or B target disconnect after the first data phase, forcing the external
master to perform a single word transfer as per the PCI specification.
The arming/disarming of the INS/EXT bits provides a switch debounce
function.
Mindspeed Technologies
11.2 Unimplemented PCI Bus Interface Functions
™
11.0 PCI Bus Interface
11-3