CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 187

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
6.2.4 VBR Traffic
28236-DSH-001-B
VBR Service Categories
6.2.4.2 Rate-Shaping
6.2.4.3 Single Leaky
Categories to TM 4.1
CN8236 VBR Service
6.2.4.4 Dual Leaky
6.2.4.1 Mapping
vs. Policing
Bucket
Bucket
The CN8236 Cell Scheduler also supports multiple priority levels for VBR
traffic. The VBR service class takes advantage of the asynchronous nature of
ATM by reserving bandwidth for VBR channels at average cell transmission rates
without hardcoding time slots, as with CBR traffic. This dynamic scheduling
allows VBR traffic to be statistically multiplexed onto the ATM line, resulting in
better use of the shared bandwidth resources.
The ATM Forum TM 4.1 Specification describes the different categories of VBR
service in a different manner than is employed in the CN8236 device. These
relationships are described in
Table 6-4. CN8236 VBR to TM 4.1 VBR Mapping
The Cell Scheduler rate-shapes the segmentation traffic for up to 64 K
connections. The outgoing cell stream for each VCC is scheduled according to
the GCRA algorithm. This guarantees compliance to policing algorithms applied
at the network ingress point. Channels can be rate-shaped as VCs or VPs,
according to one of three leaky bucket paradigms, set by the SCH_MODE bit in
the channel’s segmentation VCC table entry.
The first and simplest bucket scheme is single leaky bucket. The user defines a
single set of GCRA parameters — I (Interval) and L (Limit). I is used to control
the per-VCC PCR, and L is used to control the CDVT of the outgoing cell stream.
The user enables this scheme by setting the SCH_MODE bits to 100 (VBR1).
The user can also select, on a per-VCC basis, to apply two leaky buckets to a
single connection. The user enables this scheme by setting the SCH_MODE bits
to 101 (VBR2).
parameters. These parameters are stored as bucket table entries. (See
for the definition of a bucket table entry.) There is complete flexibility with
regard to using these 256 values to specify SCR or PCR. In VBR2, I1 and L1 can
specify either PCR and CVDT, or SCR and Burst Tolerance (BT), with I2 and L2
used to specify the parameters not assigned to I1 and L1.
VBR1
VBR2
VBR3 (or VBRC)
CN8236 VBR
When using VBR2 SCH_MODE, the limitation is 256 values for the I2 and L2
For example, to configure
or
Mindspeed Technologies
I1 = PCR, L1 = CDVT, I2 = SCR, L2 = BT
I1 = SCR, L1 = BT, I2 = PCR, L2 = CDVT
(None)
VBR.1
VBR.2 /VBR.3
TM 4.1 VBR
Table
TM 4.1 does not employ single leaky bucket.
Double leaky bucket.
TM 4.1 defines two conformance standards for
CLP(0+1).
6-4.
™
6.2 xBR Cell Scheduler Functional Description
Comments
6.0 Traffic Management
Table
6-14,
6-19