CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 291

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

28236-DSH-001-B
12.0 ATM UTOPIA Interface
12.1 Overview of ATM UTOPIA Interface
The ATM UTOPIA interface contains receive and transmit interface logic and
receive error detection logic. The ATM UTOPIA interface block also interfaces
with the segmentation and reassembly coprocessors.
segmentation coprocessor and transmits them to the PHY device while inserting a
dummy HEC. The interface also receives 53 octet cells from the PHY device,
removes the HEC, and saves them in a FIFO buffer to be used by the reassembly
coprocessor.
controlling the ATM link interface device, which carries out all the transmission
convergence and physical media-dependent functions defined by the ATM
protocol. The block performs the following functions:
The ATM UTOPIA interface for the CN8236 accepts 52 octet cells from the
The ATM UTOPIA interface is responsible for communicating with and
• Receives and transmits ATM UTOPIA interface logic. The ATM UTOPIA
• Receives cell synchronization logic, which validates cell boundaries in the
• Transmits cell synchronization logic, which converts the 32-bit data read
• Generates and checks odd parity on the octet transmit and receive data
• Programmable single/separate UTOPIA clock via CONFIG1 register
interface accommodates Mindspeed RS825x, RS8228, or Bt8223 physical
layer devices, a UTOPIA-compatible framer or a Mindspeed-conceived
slave UTOPIA interface, and is responsible for converting between these
devices and the internal data interfaces. The Slave UTOPIA interface
connects the CN8236 to a cell-switched backplane.
incoming byte stream, strips off the HEC byte from the ATM header, and
formats the remaining 52 bytes into thirteen 32-bit words before passing
them to the incoming cell FIFO buffer. The receive cell synchronization
logic ensures that only complete cells are passed down to the remainder of
the reassembly controller.
from the transmit cell FIFO buffer into 8- or 16-bit (plus parity) streams,
generates appropriate cell delineation pulses for use by the transmit ATM
UTOPIA interface, and inserts the blank HEC byte into the ATM header of
each cell prior to transferring it to the UTOPIA interface.
buses.
bit 23.
Mindspeed Technologies
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