CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 102

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

Table 4-16. Transmit Queue Base Table Entry
4.0 Segmentation Coprocessor
4.3 Segmentation Control and Data Structures
4-24
Table 4-17. Transmit Queue Base Table Entry Field Descriptions
Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4.3.4.2 Transmit Queue
READ_UD_PNTR
LOCAL
UPDATE
READ
0
1
Field Name
Management
Reserved
Points to READ_UD used by host to prevent queue overflow. The SAR writes its read pointer into the
queue to this address periodically. (See
0 = READ_UD located in PCI address space.
1 = READ_UD located in SAR-shared memory.
NOTE(S):
SAR position in update interval. Number of queue entries processed since last update of READ_UD.
SAR read pointer. Represents the SAR’s current position in the transmit queue.
The transmit queues reside in a single continuous section of SAR-shared memory.
During initialization the host configures the number of entries per queue with the
SEG_CTRL(TR_SIZE) field. The size ranges from 64 to 4,096 entries per queue.
The host also selects a priority scheme at initialization with the
SEG_CTRL(TX_RND) bit. Both of these fields are static configurations and
must not be changed during runtime operation.
address of all active transmit queues. This register contains the base address of the
first queue, the number of active queues, and the write-only update interval for all
queues. A set of other internal registers, the Transmit Queue Base table entries,
tracks the current state of the queues.
the fields of these queues.
queue.
queue. The transmit queue base table contains all of the queue control variables
except for INTERVAL, which is located in the SEG_TXBASE register.
For write-only PCI host interfaces, this bit should be set low.
By initializing the SEG_TXBASE register, the host determines the base
The byte address of any transmit queue entry is given by:
The host manages each transmit queue as an independent write-only control
Chapter 3.0
Mindspeed Technologies
(SEG_TXBASE(SEG_TXB) 128)
UPDATE
<decoded TQ_SIZE value
READ_UD_PNTR
describes the runtime management of a write-only control
Chapter
ATM ServiceSAR Plus with xBR Traffic Management
Description
Reserved
2.0, for details.)
+
Table 4-16
<entry number> 4
™
+
<transmit queue number>
and
Table 4-17
READ
28236-DSH-001-B
below describe
CN8236