CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 376

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

15.0 SAR Initialization—Example Tables
15.4 General Initialization
Table 15-9. Table of Values for General Control Register Initialization (2 of 2)
15-16
HOST_ST_WR
(Host Status Write Register)
HOST_ISTAT1
(Host Interrupt Status Register 1)
HOST_ISTAT0
(Host Interrupt Status Register 0)
LP_ISTAT1
(Local Interrupt Status Register 1)
LP_ISTAT0
(Local Interrupt Status Register 0)
HOST_IMASK1
(Host Interrupt Mask Register 1)
HOST_IMASK0
(Host Interrupt Mask Register 0)
LP_IMASK1
(Local Interrupt Mask Register 1)
LP_IMASK0
(Local Interrupt Mask Register 0)
PCI Configuration Space
PCI COMMAND Register
PCI STATUS Register
PCI SPECIAL_STATUS Register
PCI EEPROM Register
Register
RSM_HS_WRITE
RSM_LS_WRITE
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
COMMAND
LAT_TIMER
BASE_ADDRESS_
REGISTER_0
INTERRUPT_LINE
(ALL OTHER FIELDS)
FB_EN
SE_EN
PE_EN
M_EN
MS_EN
—
—
—
Mindspeed Technologies
Field
0x8700FC07
0x4040000F
Initialized
0x0346
Value
0x10
0x01
0x00
ATM ServiceSAR Plus with xBR Traffic Management
0x0
0x0
—
—
—
—
—
—
—
—
—
—
1
1
1
1
1
™
Read twice after SAR reset.
Read twice after SAR reset.
Read twice HOST_ST_WR reset.
Read twice HOST_ISTAT1 reset.
Read twice SAR reset.
Read twice LP_ISTAT1 reset.
Enable interrupts in errors, counter
relievers and framer interrupt.
Local processor not used.
Local processor not used.
Enable all functions of PCI interface.
Latency timer = 16 clock periods.
Base address of SAR device in PCI memory
space is 0x0100_0000.
Interrupt vector = 0.
Hard-coded reads only.
Enable master fast back-to-back across
target.
Enable SERR* output pin.
Enable parity error detection and report.
Enable CN8236 device master on the PCI
bus.
Enable CN8236 memory space access
across the PCI bus.
(No initialization required.)
(No initialization required.)
(No initialization required.)
Enable all errors to cause an interrupt.
Notes
28236-DSH-001-B
CN8236