CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 319

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 14-2. CN8236 Control and Status Registers (2 of 2)
28236-DSH-001-B
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C–0x15C
0x160
0x164
0x168
0x16C
0x170–0x19C
0x1a0
0x1a4
0x1a8
0x1ac
0x1b0
0x1b4–0x1bc
0x1c0
0x1c4
0x1c8–0x1cc
0x1d0
0x1d4
0x1d8–0x1dc
0x1e0
0x1e4
0x1e8–0x1ec
0x1f0
0x1f4
0x1f8–0x1fc
Address
RSM_TO
RS_QBASE
ERS_BASE
VPI_SIZE
TX_FIFO_CTRL
TX_PORT_CTRL
Reserved
CELL_XMIT_CNT
CELL_RCVD_CNT
CELL_DSC_CNT
AAL5_DSC_CNT
Reserved
HOST_MBOX
HOST_ST_WR
AALx_STAT
TX_STATUS
LP_MBOX
Reserved
HOST_ISTAT0
HOST_ISTAT1
Reserved
HOST_IMASK0
HOST_IMASK1
Reserved
LP_ISTAT0
LP_ISTAT1
Reserved
LP_IMASK0
LP_IMASK1
Reserved
Name
Mindspeed Technologies
R/W
R/W
R/W
R/W
R/W
R/W
—
R/O
R/O
R/O
R/O
—
R/W L
R/O
R/O
R/O
R/W H
—
R/O
R/O
—
R/W H
R/W H
—
R/O
R/O
—
R/W L
R/W L
—
Type
Reassembly Time-out register
Reassembly/Segmentation Queue Base register
Reassembly ER_SHIFT Tables Base register
Variable VPI Size register
Transmit Port Register
Transmit Port Control register
Not Implemented
ATM Cells Transmitted Counter
ATM Cells Received Counter
ATM Cells Discarded Counter
AAL5 PDUs Discarded Counter
Not Implemented
Host Mailbox register
Host Status Write register
AALx Counter Status register
Tx Port Cell Discard Status register
Local Processor Mailbox register
Not Implemented
Host Interrupt Status register 0
Host Interrupt Status register 1
Not Implemented
Host Interrupt Mask register 0
Host Interrupt Mask register 1
Not Implemented
Local Processor Interrupt Status register 0
Local Processor Interrupt Status register 1
Not Implemented
Local Processor Interrupt Mask register 0
Local Processor Interrupt Mask register 1
Not Implemented
™
Description
14.1 Control and Status Registers
14.0 CN8236 Registers
14-3