CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 307
CN8236EBGB
Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236EBGB.pdf
(443 pages)
Specifications of CN8236EBGB
Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
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CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Figure 12-7. Transmit Timing in Slave UTOPIA Level 1 Mode
28236-DSH-001-B
TXD/TXPAR
(TXFLAG*)
(TXMARK)
NOTE(S):
(1)
(2)
(3)
(4)
TXCLAV
TXSOC
TXCLK
TXEN*
TXCLAV goes active when a complete cell is in the transmit FIFO buffer.
Example of physical device deactivating TXEN*.
The TXD/TXPAR and TXSOC lines are three-stated (floated) when TXEN* is sampled high (de-asserted).
Physical device can keep TXEN* active while TXCLAV is inactive.
(1)
TxEN* is sampled asserted. Simultaneously, the 8-bit odd parity computed over
the TxData[15:0] lines is driven on to the TxPar output. The TxSOC line is driven
by the SAR to indicate start of cell. If the TxClav output is asserted by the
CN8236, the transmit FIFO buffer does not contain a complete cell. (See
Figure
H1
Transmit data is driven on TxData[15:0] on the rising edge of TXCLK after
12-7.)
***
Mindspeed Technologies
H5
P1
P2
(2)
(3)
(3)
P3
™
***
P48
12.7 Slave Level 1 UTOPIA Mode
(4)
12.0 ATM UTOPIA Interface
H1
H2
8236_076
12-17
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