CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 19
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CN8236EBGB
Manufacturer Part Number
CN8236EBGB
Description
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8236EBGB.pdf
(443 pages)
Specifications of CN8236EBGB
Package
388BGA
Traffic Class
ABR|CBR|GFR|UBR|VBR
Utopia Type
Level 1|Level 2
Host Interface
PCI
Maximum Data Rate
155 Mbps
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CN8236EBGB
Manufacturer:
VIA
Quantity:
150
Company:
Part Number:
CN8236EBGB
Manufacturer:
CONEXANT
Quantity:
329
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CN8236
ATM ServiceSAR Plus with xBR Traffic Management
List of Figures
28236-DSH-001-B
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10.
Figure 5-11.
Figure 5-12.
Figure 5-13.
CN8236 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Multiple Client Architecture Supports Up To 32 Clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
CN8236 Queue Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Interaction of Queues with CN8236 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Reassembly Buffer Isolation—Data Buffers Separated from Descriptors . . . . . . . . . . . . . . 2-6
Segmentation Buffer Isolation—Data Buffers Separated from Descriptors . . . . . . . . . . . . . 2-7
Segmentation Status Queues Related to Data Buffers and Descriptors . . . . . . . . . . . . . . . . 2-8
Reassembly Status Queues Related to Data Buffers and Descriptors . . . . . . . . . . . . . . . . . 2-9
Write-Only Control and Status Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Multi-Level Model for Prioritizing Segmentation Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Data FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
CN8236 Logic Diagram (1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Client/Server Model of the CN8236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Peer-to-Peer vs. Centralized Memory Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Out-of-Band Control Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Write-only Control Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Write-only Status Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Segmentation VCC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Segmentation Buffer Descriptor Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Before SAR Transmit Queue Entry Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
After SAR Transmit Queue Entry Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
AAL5 CPCS-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
AAL3/4 CPCS-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Route Tag Table for tag_size = 1 through 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Route Tag Table for tag_size = 5 through 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Route Tag Table for tag_size = 9 through 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Reassembly—Basic Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Reassembly VCC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Direct Index Method for VPI/VCI Channel Lookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Programmable Block Size Alternate Direct Index Method . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Direct Index Lookup Method for AAL3/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
VPI Index Table with Multiple Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
CPCS-PDU Reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
AAL5 EOM Cell Processing—Fields to Status Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
AAL5 Processing—CRC and PDU Length Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
AAL3/4 CPCS—PDU Reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
AAL0 PTI PDU Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Host and SAR-Shared Memory Data Structures for Scatter Method . . . . . . . . . . . . . . . . . 5-19
Free Buffer Queue Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Mindspeed Technologies
™
List of Figures
19
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