CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 353

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
This register contains the interrupt enables that correspond to the status in the LP_ISTAT0 register. The
assertion of the HRST* system reset pin clears all of the LP_IMASK0 interrupt enables.
Table 14-9. 0x1f0—Local Processor Interrupt Mask Register 0 (LP_IMASK0)
28236-DSH-001-B
25–24
21–19
14–12
8–4
Bit
31
30
29
28
27
26
23
22
18
17
16
15
11
10
9
3
2
1
0
Field
Size
1
1
1
1
1
1
2
1
1
3
1
1
1
1
3
1
1
1
5
1
1
1
1
EN_RTC_OVFL
EN_ALARM1
Reserved
EN_LP_MBOX_WRITTEN
EN_HOST_MBOX_READ
Reserved
Reserved
Reserved
EN_LSTAT1
Reserved
EN_GFC_LINK
EN_RSM_RUN
EN_RSM_HS_WRITE
EN_RSM_LS_WRITE
Reserved
EN_SEG_RUN
EN_SEG_HS_WRITE
EN_SEG_LS_WRITE
Reserved
EN_AAL5_DSC_RLOVR
EN_CELL_DSC_RLOVR
EN_CELL_RCVD_RLOVR
EN_CELL_XMIT_RLOVR
Name
Mindspeed Technologies
Enables an interrupt when RTC_OVFL status is a logic high.
Enables an interrupt when ALARM1 status is a logic 1.
Set to 0.
Enables an interrupt when LP_MBOX_WRITTEN status is a logic 1.
Enables an interrupt when HOST_MBOX_READ status is a logic 1.
Set to 0.
Set to 0.
Set to 0. Reserved for future status page expansion.
Global interrupt enable for LP_ISTAT1 status register. Individual
interrupts of LP_ISTAT1 are enabled in LP_IMASK1.
Set to 0.
Enables an interrupt when GFC_LINK status is a logic 1.
Enables an interrupt when RSM_RUN status is a logic 1.
Enables an interrupt when RSM_HS_WRITE status is a logic high.
Enables an interrupt when RSM_LS_WRITE status is a logic high.
Set to 0.
Enables an interrupt when SEG_RUN status is a logic high.
Enables an interrupt when SEG_HS_WRITE status is a logic high.
Enables an interrupt when SEG_LS_WRITE status is a logic high.
Set to 0.
Enables an interrupt when AAL5_DSC_RLOVR status is a logic high.
Enables an interrupt when CELL_DSC_RLOVR status is a logic high.
Enables an interrupt when CELL_RCVD_RLOVR status is a logic high.
Enables an interrupt when CELL_XMIT_RLOVR status is a logic high.
™
Description
14.6 Counters and Status Registers
14.0 CN8236 Registers
14-37