CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 343

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
0x16c
This register counts the number of AAL5 CPCS-PDUs discarded due to buffer firewall, buffer underflow, or
status overflow. The counter is reset to 0 by an assertion of either the HRST* system reset pin or the
GLOBAL_RESET bit in the CONFIG0 register. Optionally, an interrupt can be programmed when the counter
rolls over.
0x1a0
This register implements a mailbox for communication between the host and local processors. The register is
written by the local processor and read by the host to pass messages in that direction. Writes to this register can
interrupt the host, while reads can interrupt the local processor.
0x1a4
This register indicates if a reassembly or segmentation host-located status queue has been written. Only queues
0 through 15 are supported. All bits are latched until read by the host. The RSM_HS_WRITE[15:0] bits are
ORed together into HOST/LP_ISTAT0(RSM_HS_WRITE), and the SEG_HW_WRITE[15:0] bits are ORed
together into HOST/LP_ISTAT0(SEG_HS_WRITE).
28236-DSH-001-B
31–16
31–16
15–0
31–0
15–0
Bit
Bit
Bit
—
—
—
AAL5 PDUs Discarded Counter (AAL5_DSC_CNT)
Host Mailbox Register (HOST_MBOX)
Host Status Write Register (HOST_ST_WR)
Field
Field
Field
Size
Size
Size
16
16
32
16
16
Reserved
AAL5_DSC_CNT
HOST_MBOX[31:0]
RSM_HS_WRITE[15:0]
SEG_HS_WRITE[15:0]
Name
Name
Name
Mindspeed Technologies
Not implemented at this time.
AAL5 PDUs discarded by the reassembly coprocessor.
Messages flow from local processor to host.
Indication that a host-located reassembly status queue entry has
been written. Only queues 0 through 15 are supported.
Indication that a host-located segmentation status queue entry has
been written. Only queues 0 through 15 are supported.
™
Description
Description
Description
14.6 Counters and Status Registers
14.0 CN8236 Registers
14-27