CN8236EBGB Mindspeed Technologies, CN8236EBGB Datasheet - Page 357

• Manufacturer Part Number: CN8236EBGB
• Description: ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8236EBGB

• Package: 388BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 155 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
Table 14-12. PCI Register Configuration Register Field Descriptions (2 of 2)
28236-DSH-001-B
SPECIAL_STATUS
_REGISTER
MASTER_READ
_ADDR
MASTER_WRITE
_ADDR
EEPROM_REGISTER
PM_CAPABILITY
NEXT_CAP_PTR
CAPABILITY_ID
PM_DATA
PMCSR
Bit
Device status not defined by the PCI specification. (The field is further subdivided into subfields as
described in
specification. The configuration registers are accessed starting from byte address 0 in the
configuration space allotted to an adapter card containing the SAR chip. Access to the configuration
registers is available only to the PCI host CPU, and is independent of all other SAR logic.
Current read target address used by PCI bus master (read only).
Current write target address used by PCI bus master (read only).
A 32-bit register controlling access to the Serial EEPROM. (See
specific fields in the EEPROM_REGISTER.)
Power Management Capabilities register. A 16-bit read-only register which provides information on the
capabilities of the function related to Power Management. See the PCI Bus Power Management
Interface Specification Revision 1.0 for specific information related to this register.
Next Item Pointer register. This field provides an offset into the PCI Configuration space pointing to the
location of the next item of the linked capability list. If there are no additional items in the Capabilities
List, this register is set to 0x00.
Capability Identifier. When set to 0x01, indicates that the linked list item being pointed to is the PCI
Power Management registers. Default value is 0x01.
Power Management Data register. This 8-bit read-only register provides a mechanism for the Power
Management function to report state-dependent operating data, such as power consumed or heat
dissipation. See the PCI Bus Power Management Interface Specification Revision 1.0 for specific
information related to this register.
Power Management Control/Status register. This 16-bit register is used to manage the PCI function’s
power management state, and to enable and monitor power management events. See the PCI Bus
Power Management Interface Specification Revision 1.0 for specific information related to this register.
Table
Mindspeed Technologies
14-15.) Detailed descriptions of these subfields can be found in the PCI bus
Description
™
Table 14-16
14.7 PCI Bus Interface Registers
for a description of the
14.0 CN8236 Registers
14-41