PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 78
PEB2255H-V13
Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2255H-V13.pdf
(374 pages)
Specifications of PEB2255H-V13
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN
PEB2255H-V13IN
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Manufacturer
Quantity
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Part Number:
PEB2255H-V13
Manufacturer:
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• XBS1/0 = 11 : short buffer or 92 bits :
The functions of the transmit buffer are:
• Clock adaption between system clock (SCLKX) and internally generated transmit
• Compensation of input wander and jitter.
• Frame alignment between system frame and transmit line frame
• Reporting and controlling of slips
Writing of received data from XDI is controlled by SCLKX and SYPX/XMFS in
conjunction with the programmed offset values for the transmit time slot/clock slot
counters. Reading of stored data is controlled by the clock generated by DCO-X circuitry
and the transmit framer. With the dejittered clock data is read from the transmit elastic
buffer and are forwarded to the transmitter. Reporting and controlling of slips is done
according to the receive direction. Positive/negative slips are reported in interrupt status
bits ISR5.XSP and ISR5.XSN. If the transmit buffer is bypassed data is directly
transferred to the transmitter.
The following table gives an overview of the transmit buffer operating modes.
Table 15
SIC1.XBS1...0
00
11
01
10
4.3.3
The serial bit stream is then processed by the transmitter which has the following
functions:
• Frame/multiframe synthesis of one of the two selectable framing formats
• Insertion of service and data link information
• AIS generation (Alarm indication signal)
• Remote alarm generation
• CRC generation and insertion of CRC bits
• CRC bits inversion in case of a previously received CRC error
• IDLE code generation per DS0
Data Sheet
Max. wander amplitude: 18 µs
clock (XCLK).
average delay after performing a slip: 46 bits
Transmitter (E1)
Transmit Buffer Operating Modes (E1)
Buffer Size
bypass
short buffer
1 frame
2 frames
78
TS Offset
programming
enabled
enabled
enabled
enabled
Functional Description E1
Slip performance
no
yes
yes
yes
If XSW.XTM = 1,
slip is performed on
the frame boundary
FALC-LH V1.3
PEB 2255
2000-07
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