PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 154

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

5.6.3
To perform an effective circuit test a line loop is implemented.
If the payload loopback (FMR2.PLB) is activated the received 192 bits of payload data
is looped back to the transmit direction. The framing bits, CRC6 and DL bits are not
looped, if FMR4.TM = 0. They are originated by the FALC
1 the received FS/DL bit is sent transparently back to the line interface. Following pins
are ignored: XDI, XSIG, SCLKX, SYPX and XMFS. All the received data is processed
normally. With bit FMR2.SAIS an AIS can be sent to the system interface via pin RDO.
Figure 53
Note: Returned data is not multiframe synchronous.
Data Sheet
RL1
RL2
XL1
XL2
Payload Loop Back
Payload Loop (T1/J1)
Clock +
Data
Recovery
Trans.
Framer
RCLK
Rec.
Framer
154
Elast.
Store
Elast.
Store
Functional Description T1/J1
®
-LH transmitter. If FMR4.TM=
AIS-GEN
MUX
FALC-LH V1.3
PEB 2255
RDO
SCLKR
XDI
SCLKX
ITS09748
2000-07