PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 145

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

5.4.6.1
In the synchronous state terminal framing (FT bits) and multiframing (FS bits of the
framing header) are observed independently. Further reaction on framing errors
depends on the selected synchronization/resynchronization procedure (via bit
FMR2.SSP):
• FMR2.SSP = ‘0’: terminal frame and multiframe synchronization are combined
• FMR2.SSP = ‘1’: terminal frame and multiframe synchronization are separated
Data Sheet
Two errors within 4/5/6 framing bits (via bits FMR4.SSC1/0) of one of the above lead
to the asynchronous state for terminal framing and multiframing. Additionally to the
resynchronization procedure starts with synchronizing upon the terminal framing. If
the pulse framing has been regained, the search for multiframe alignment is initiated.
Multiframe synchronization has been regained after two consecutive correct
multiframe patterns have been received.
Two errors within 4/5/6 terminal framing bits lead to the same reaction as described
above for the “combined” mode.
Two errors within 4/5/6 multiframing bits lead to the asynchronous state only for the
multiframing. Loss of multiframe alignment is reported via bit FRS0.LMFA. The state
of terminal framing is not influenced.
Now, the resynchronization procedure includes only the search for multiframe
alignment. Multiframe synchronization has been regained after two consecutive
correct multiframe patterns have been received.
Synchronization Procedure
145
Functional Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07