PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 161

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

•
Table 41
Register
FMR0.XC0
FMR0.RC0
LIM1.DRS
FMR3.CMI
PCD = 0A
PCR = 15
LIM1.RIL2-0 = 03
E1 Framer Initialization
The selection of the following modes during the basic initialization supports the ETSI
requirements for E-Bit Access, Remote Alarm and Synchronization (please refer also to
FALC
and helps to reduce the software load. They are very helpful especially to meet
requirements as specified in ETS300 011.
Table 42
Register
XSP.AXS = 1
XSP.EBP = 1
FMR2.AXRA = 1
FMR2.FRS1/2 = 10
FMR1.AFR = 1
Data Sheet
®
-LH driver code of the Reference System EASY2255-R1 and application notes)
H
H
Line Interface Initialization (E1)
Framer Initialization (E1)
H
Function
ETS300 011 C4.x for instance requires the sending of E-Bits in
TS0 if CRC4 errors have been detected. By programming
XSP.AXS = 1 the submultiframe status is inserted automatically in
the next outgoing multiframe.
If the FALC
cleared if XSP.EBP = 0 and set if XSP.EBP = 1. ETS300 011
requires that the E-Bit is set in asynchronous state.
The transmission of RAI via the line interface is done automatically
by the FALC
(FRS0.LFA = 1). If basic framing has been reinstalled RAI is
automatically reset.
In this mode a search of double framing is automatically reinitiated
if no CRC4 multiframing could be found within 8ms. Together with
FMR2.AXRA = 1 this mode is essential to meet ETS300 011 and
reduces the processor load heavily.
Function
The FALC
interface as well as the digital line interface. For the analog line
interface the codes AMI and HDB3 are supported. For the digital
line interface modes (dual or single rail) the FALC
AMI, HDB3, CMI (with and without HDB3 precoding) and NRZ.
LOS detection after 176 consecutive “zeros” (fulfills G.775 spec).
LOS recovery after 22 “ones” in the PCD interval. (fulfills G.775).
LOS threshold (fulfills G.775; see DC characteristics)
®
®
-LH supports requirements for the analog line
-LH has reached asynchronous state the E-Bit is
®
-LH in case of Loss of Frame Alignment
161
Operational Description E1
FALC-LH V1.3
®
-LH supports
PEB 2255
2000-07