PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 176

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

8.3.9
The FALC
• access via registers RSW/XSW
• access via registers RSA8-4/XSA4-8
• capable of storing the information for a complete multiframe
the access via the 64 byte deep receive/transmit FIFO of the integrated signaling
controller. This S
stream as well as HDLC frames where the signaling controller automatically processes
the HDLC protocol. Enabling for receive direction is done by resetting of CCR1.EITS=0
and setting of registers XCO.SA4E...8E as required. For transmit direction bits
TSWM.TSA4...8 have to be set as required, additionally.
Data written to the XFIFO will subsequently transmit in the S
register XC0.SA8E-4E and the corresponding bits of TSWM.TSA8-4. Any combination
of S
Flags (CCR1.ITF) are transmitted. The continuous transmission of a transparent bit
stream, which is stored in the XFIFO, can be enabled.
With the setting of bit MODE.HRAC the received S
FIFO.
The access to and from the FIFOs is supported by ISR0.RME/RPF and ISR1.XPR/ALS.
8.3.10
The FALC
Interfaces using the Extended Super Frame format. The device supports the DL-channel
protocol for ESF format according to T1.403-1989 ANSI or to AT&T TR54016
specification. The HDLC- and Bit Oriented Message (BOM) -Receiver can be switched
on/off independently. If the FALC
has to be switched off. If HDLC- and BOM-receiver has been switched on
(MODE.HRAC/BRAC), an automatic switching between HDLC and BOM mode is
enabled. Storing of received DL bit information in the RFIFO of the signaling controller
and transmitting the XFIFO contents in the DL bit positions is enabled by CCR1.EDLX/
EITS = 10. After hardware (pin RES = high) or software reset (CMDR.RRES = 1) the
FALC
BOM mode is entered. Upon detection of a flag in the data stream, the FALC
switches back to HDLC-mode. Operating in BOM-mode, the FALC
HDLC frame immediately, i.e. without any preceding flags.
In BOM-mode, the following byte format is assumed (the left most bit is received first).
111111110xxxxxx0
The FALC
(first bit received: LSB) if it starts and ends with a ‘0’. Bytes starting and ending with a ‘1’
are not stored. If there are no 8 consecutive one’s detected within 32 bits, an interrupt
ISR0.ISF is generated. However, byte sampling is not stopped.
Data Sheet
a
®
bits can be selected. After the data has been sent out completely, “all ones” or
-LH operates in HDLC mode. If eight or more consecutive ones are detected, the
®
®
®
-LH supports the S
S
Bit Oriented Message Mode (T1/J1)
-LH supports signaling and maintenance functions for T1/J1 - Primary Rate
-LH uses the FF
a
bit Access (E1)
a
bit access gives the opportunity to transmit/receive a transparent bit
H
byte for synchronization, the next byte is stored in RFIFO
a
bit signaling of time slot 0 of every other frame as follows:
®
-LH is used for HDLC formats only, the BOM receiver
176
Signaling Controller Operating Modes
a
bits can be forwarded to the receive
a
bit positions defined by
®
-LH may receive an
FALC-LH V1.3
PEB 2255
2000-07
®
-LH