PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 313
![IC INTERFACE LINE 80-MQFP](/photos/6/94/69416/peb2255h-v13_sml.jpg)
PEB2255H-V13
Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2255H-V13.pdf
(374 pages)
Specifications of PEB2255H-V13
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN
PEB2255H-V13IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Data Sheet
PRBS Status
LCR1.EPRM=1: The current status of the PRBS synchronizer is
indicated in this bit. It is set high if the synchronous state is reached
even in the presence of a BER 1/10. A data stream containing all
zeros with/without framing bits is also a valid pseudo random bit
sequence. The same applies to an all ones data stream, if PRBS data
inversion is selected.
Transmit Line Short
Significant only if the ternary line interface is selected by
LIM1.DRS=0.
0…
Transmit Line Open
0…
1…
1…
Normal operation. No short is detected.
The XL1 and XL2 are shortened for at least 32 pulses. As a
reaction of the short the pins XL1 and XL2 are automatically
forced into a high impedance state if bit XPM2.DAXLT is reset.
After 32 consecutive pulse periods the outputs XL1/2 are
activated again and the internal transmit current limiter is
checked. If a short between XL1/2 is still further active the
outputs XL1/2 are in high impedance state again. When the
short disappears pins XL1/2 are activated automatically and
this bit is reset. With any change of this bit an interrupt
ISR1.XLSC is generated. In case of XPM2.XLT is set this bit is
frozen.
Pins XL1M and XL2M have to be connected to XL1 and XL2,
respectively.
Normal operation
This bit is set if at least 32 consecutive zeros were sent via pins
XL1/XL2 respective XDOP/XDON. This bit is reset with the first
transmitted pulse. With the rising edge of this bit an interrupt
ISR1.XLSC is set. In case of XPM2.XLT is set this bit is frozen.
313
FALC-LH V1.3
T1/J1 Registers
PEB 2255
2000-07
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