PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 66

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

4.1.12
The signaling controller can be programmed to operate in various signaling modes. The
FALC
4.1.12.1 HDLC or LAPD access
In case of common channel signaling the signaling procedure HDLC/SDLC or LAPD
according to Q.921 is supported. The signaling controller of the FALC
FLAG detection, CRC checking, address comparison and zero bit-removing. The
received data flow and the address recognition features can be performed in very flexible
way, to satisfy almost any practical requirements. Depending on the selected address
mode, the FALC
is selected, the high address byte is compared with the fixed value FEH or FCH (group
address) as well as with two individually programmable values in RAH1 and RAH2
registers. According to the ISDN LAPD protocol, bit 1 of the high byte address is
interpreted as command/response bit (C/R) and is excluded from the address
comparison. Buffering of receive data is done in a 64 byte deep RFIFO.
In signaling controller transparent mode, fully transparent data reception without HDLC
framing is performed, i.e. without FLAG recognition, CRC checking or bit-stuffing. This
allows user specific protocol variations.
The FALC
combination of time slots may be programmed independently for the receive and
transmit direction.
4.1.12.2 S
The FALC
• the access via register RSW
• the access via registers RSA4-8, capable of storing the information for a complete
• the access via the 64 byte deep receive FIFO of the signaling controller. This S
4.1.12.3 Channel Associated Signaling CAS (E1, serial mode)
The signaling information is carried in time slot 16 (TS16). The signaling controller
samples the bit stream on the receive system side (selected by setting LOOP.SPN=1,
LIM3.ESY=1).
Data Sheet
multiframe
access gives the opportunity to receive a transparent bit stream as well as HDLC
frames where the signaling controller automatically processes the HDLC protocol.
Any combination of S
be selected by XC0.SA8E-SA4E. The access to the RFIFO is supported by
ISR0.RME/RPF.
®
-LH performs the following signaling and data link methods:
®
®
-LH supports the S
Receive Signaling Controller (E1)
-LH offers the flexibility to extract data during certain time slots. Any
a
bit Access (E1)
®
-LH performs a 1 or 2 byte address recognition. If a 2-byte address field
a
bits which should be extracted and stored in the RFIFO may
a
bit signaling of time slot 0 of every other frame as follows:
66
Functional Description E1
®
-LH performs the
FALC-LH V1.3
PEB 2255
2000-07
a
bit