PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 205

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

CRCI…
XCRCI…
RDIS…
RCO2...0…
Data Sheet
Automatic CRC4 Bit Inversion
If set, all CRC bits of one outgoing submultiframe are inverted in case
a CRC error is flagged for the previous received submultiframe. This
function is logically ORed with RC0.XCRCI.
Transmit CRC4 Bit Inversion
If set, the CRC bits in the outgoing data stream are inverted before
transmission. This function is logically ORed with RC0.CRCI.
Receive Data Input Sense
Only applicable for dual rail mode (LIM1.DRS = 1).
0… Inputs: RDIP, RDIN active low, input ROID is active high
1… Inputs: RDIP, RDIN active high, input ROID is active low
Receive Clock Slot Offset/Receive Frame Marker Offset
Depending on bit SIC2.SRFSO this bit enables different functions:
Receive Clock-Slot Offset (SIC2.SRFSO = 0)
Initial value loaded into the receive bit counter at the trigger edge of
SCLKR when the synchronous pulse on port SYPR is active.
Receive Frame Marker Offset (SIC2.SRFSO = 1)
Offset programming of the receive frame marker which is output on
port SYPR. The receive frame marker could be activated during any
bit position of the current frame.
Calculation of the value X of the “Receive Counter Offset” register
RC1/0 depends on the bit position BP which should be marked and
SCLKR:
X = (2 + 2 BP) mod 512, for SCLKR = 2.048 MHz.
205
FALC-LH V1.3
E1 Registers
PEB 2255
2000-07