PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 300

IC INTERFACE LINE 80-MQFP

PEB2255H-V13

Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB2255H-V13

Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
System Interface Control 1 (Read/Write)
Value after RESET: 00
SRSC…
RBS1…0…
Data Sheet
SIC1
SRSC
7
Select Receive System Clock
0…
1…
Receive Buffer Size
00… Buffer size: 2 frames
01… Buffer size: 1 frame
10… Buffer size: 92 bits
11… Bypass of receive elastic store
H
Input frequency on pin SCLKR: 8.192 MHz
Calculation of delay time T (SCLKR cycles) depends on the
value X of the “Receive Counter Offset” register RC1/0 and of
the programming of RC0.RCOS.
Delay T is an even number in the range of 0 to 1022:
RCOS = 0: X = 5
Input frequency on pin SCLKR: 1.544 MHz
Calculation of delay time T (SCLKR cycles) depends on the
value X of the “Receive Counter Offset” register RC1/0:
T = (196 - x/2) mod 193
Delay time T = time between beginning of time-slot 0 at RDO
and the initial edge of SCLKR after SYPR goes active.
If this bit is set FMR1.IMOD must be set also and bit RC0.0
should be cleared.
Delay T is an odd number in the range of 1 to 1023:
RCOS = 1: X = 5
RBS1
X = 517
X = 517
RBS0
300
T/2 if
(T
SXSC
T/2 if
(T
1)/2 if
0
1)/2 if
12
T
1
T
10
13
T
1022
T
XBS1
11
1023
FALC-LH V1.3
T1/J1 Registers
XBS0
0
PEB 2255
2000-07
(3C)

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