PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 28

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

•
Table 2
Pin No.
2
80
Data Sheet
Symbol
RL1
RDIP
ROID
ROID
Pin Definitions - Line Interface
Input (I)
Output (O)
Supply (S)
I (analog)
I
I
I
Line Interface Receive
Function
Line Receiver 1
Analog Input from the external transformer.
Selected if LIM1.DRS = 0.
Receive Data Input Positive
Digital input for received dual rail PCM(+) route
signal which will be latched with the internal
generated Receive Route Clock. An internal
DPLL will extract the Receive Route Clock from
the incoming data pulse. The Duty cycle of the
received signal has to be close to 50%.
The Dual Rail mode is selected if LIM1.DRS = 1
and FMR0.RC1 = 1. Input polarity is selected by
bit RC0.RDIS (after reset: active low).
Receive Optical Interface Data
Unipolar data received from fiber optical
interface with 2048 kbit/s (E1) or 1544 kbit/s (T1/
J1). Latching of data is done with the falling edge
of RCLKI. Input polarity is selected by bit
RC0.RDIS.
The Single Rail mode is selected if
LIM1.DRS = 1 and FMR0.RC1 = 0.
Receive Optical Interface Data
LOOP.SPN = 1
Unipolar data received from fiber optical
interface with 2048 kbit/s (E1) or 1544 kbit/s (T1/
J1). Latching of data is done with the falling edge
of RCLKI. Input polarity is selected by bit
RC0.RDIS.
The Single Rail mode is selected if
LIM1.DRS = 1 and FMR0.RC1 = 0.
Note: This pin contains multiple functions, see
28
also SYNC2 and XSIG.
Pin Descriptions
FALC-LH V1.3
PEB 2255
2000-07