PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 103

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Receive Short and Long Haul Interface (T1/J1)
The FALC
of a receive equalization network, noise filtering and programmable line build-outs
(LBO).
5.1.1
The FALC
up to -36 dB. The maximum reachable length with a 22 AWG twisted-pair cable is 2000
m. After Reset the FALC
to -10 dB of cable attenuation. Switching in “Long Haul“ mode is done by setting of
register LIM0.EQON.
The integrated receive equalization network recovers signals with up to -36 dB of cable
attenuation. Noise filters eliminate the higher frequency part of the received signals. The
incoming data is peak detected and sliced at 55% of the peak value to produce the digital
data stream. The received data is then forwarded to the clock & data recovery unit.
5.1.2
Status register RES reports the current receive line attenuation in a range of 0 to -36 dB
in 25 steps of approximately 1.4 dB each. The least significant 5 bits of this register
indicate the cable attenuation in dB. These 5 bits are only valid in conjunction with the
two most significant bits (RES.EV1/0 = 01).
5.1.3
The analog received signal on port RL1/2 is equalized and then peak-detected to
produce a digital signal. The digital received signal on port RDIP/N is directly forwarded
to the DPLL. The receive clock and data recovery extracts the route clock RCLK from
the data stream received at the RL1/2, RDIP/RDIN or ROID lines and converts the data
stream into a single rail, unipolar bit stream. Normally the clock that is output via pin
RCLK is the recovered clock from the signal provided by RL1/2 or RDIP/N has a duty
cycle close to 50 %. The free run frequency is defined by XTAL3 divided by 8 in periods
with no signal. The intrinsic jitter generated in the absence of any input jitter is not more
than 0.035 UI. In digital bipolar line interface mode the clock and data recovery accepts
only B8ZS or AMI coded signals with 50 % duty cycle.
5.1.4
The B8ZS line code or the AMI (ZCS) coding is provided for the data received from the
ternary or the dual rail interface. All code violations that do not correspond to zero
substitution rules are detected. The detected errors increment the code violation counter
(16 bits length). In case of the optical interface mode NRZ coding is performed
automatically and data is latched with the falling edge of pin RCLKI. When using the
Data Sheet
®
®
-LH has now an integrated short-haul and long-haul line interface, consisting
Receive Equalization Network (T1/J1)
Receive Line Attenuation Indication (T1/J1)
Receive Clock and Data Recovery (T1/J1)
Receive Line Coding (T1/J1)
-LH automatically recovers the signals received on pins RL1/2 in a range of
®
-LH is in “Short Haul“ mode, received signals are recovered up
103
Functional Description T1/J1
FALC-LH V1.3
PEB 2255
2000-07