PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 173

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

After having written 1 to 32 bytes to XFIFO, the command XREP and XTF via the CMDR
register (bit 7
in XFIFO repeatedly to the remote end.
Note: The cyclic transmission continues until a reset command (CMDR: SRES) is issued
8.3.5
As an option in HDLC mode the internal handling of received and transmitted CRC
checksum can be influenced via control bits CCR3.RCRC and CCR3.XCRC.
• Receive Direction
The received CRC checksum is always assumed to be in the 2 last bytes of a frame
(CRC-ITU), immediately preceding a closing flag. If CCR3.RCRC is set, the received
CRC checksum is written to RFIFO where it precedes the frame status byte (contents of
register RSIS). The received CRC checksum is additionally checked for correctness. If
HDLC mode is selected, the limits for ‘Valid Frame’ check are modified (refer to
description of bit RSIS.VFR).
• Transmit Direction
If CCR3.XCRC is set, the CRC checksum is not generated internally. The checksum has
to be provided via the transmit FIFO (XFIFO) as the last two bytes. The transmitted frame
will only be closed automatically with a closing flag.
The FALC
to be transmitted makes sense or not.
8.3.6
The address field of received frames can be pushed to the receive FIFO (first one or two
bytes of the frame). This function is useful with the extended address recognition. It is
enabled by setting control bit CCR2.RADD.
8.3.7
In transmit direction 2
status by polling bit SIS.XFW or after an interrupt ISR1.XPR (Transmit Pool Ready), up
to 32 bytes may be entered by the CPU to the XFIFO.
The transmission of a frame can be started by issuing an XHF command via the
command register. If enabled, a specified number of preambles (defined by register
PRE) are sent optionally before transmission of the current frame starts. If the transmit
command does not include an end of message indication (CMDR.XME), the FALC
will repeatedly request for the next data block by means of an XPR interrupt as soon as
Data Sheet
or with resetting CMDR.XREP, after which continuous ‘1’s are transmitted.
During cyclic transmission the XREP-bit has to be set with every write operation
to CMDR.
®
CRC ON/OFF Features
-LH does not check whether the length of the frame, i.e. the number of bytes
Receive Address pushed to RFIFO
HDLC Data Transmission
0 = ‘00100100’ = 24
32 byte FIFO buffers are provided. After checking the XFIFO
H
) forces the FALC
173
Signaling Controller Operating Modes
®
-LH to transmit the data stored
FALC-LH V1.3
PEB 2255
2000-07
®
-LH