PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 261
PEB2255H-V13
Manufacturer Part Number
PEB2255H-V13
Description
IC INTERFACE LINE 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2255H-V13.pdf
(374 pages)
Specifications of PEB2255H-V13
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2255H-V13
PEB2255H-V13IN
PEB2255H-V13IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PEB2255H-V13
Manufacturer:
Infineon Technologies
Quantity:
10 000
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10.2
Transmit FIFO (Write)
Writing data to XFIFO can be done in 8-bit (byte) or 16-bit (word) access. The LSB is
transmitted first.
Up to 32 bytes/16 words of transmit data can be written to the XFIFO following an XPR
(or ALLS) interrupt.
Command Register (Write)
Value after RESET: 00
RMC…
RRES…
XREP…
Data Sheet
XFIFO
CMDR
RMC
XF7
Detailed Description of T1/J1 Control Registers
7
7
Receive Message Complete
Confirmation from CPU to FALC
block has been fetched following an RPF or RME interrupt, thus the
occupied space in the RFIFO can be released.
Receiver Reset
The receive line interface except the clock and data recovery unit
(DPLL), the receive framer, the one second timer and the receive
signaling controller are reset. However the contents of the control
registers is not deleted. Receiver reset shall be done after every new
device initialization.
Transmission Repeat
If XREP is set together with XTF (write 24H to CMDR), the FALC
repeatedly transmits the contents of the XFIFO (1 32 bytes) without
HDLC framing fully transparently, i.e. without FLAG,CRC.
The cyclic transmission is stopped with an SRES command or by
resetting XREP.
Note:During cyclic transmission the XREP-bit has to be set with every
RRES
H
write operation to CMDR.
XREP
XRES
261
XHF
®
-LH that the current frame or data
XTF
XME
FALC-LH V1.3
T1/J1 Registers
SRES
XF0
0
0
PEB 2255
(00/01)
2000-07
(02)
®
-LH
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