NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 82

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer Control registers
7 0
G E N m o d u l e r e g i s t e r s
The Software Service register (SWSR) acknowledges the system watchdog timer. To
do so, firmware must write
operations. There is no restriction on the time between the two operations, but the
operations must occur in the proper sequence with the proper data values.
The Software Service register can request a software reset of the NS7520 hardware.
Firmware must write
operations. There is no restriction on the time between the two operations, and the
two operations must occur in the proper sequence with the proper data values. The
processor must be in supervisor mode for the second operation.
Register bit assignment
Table 26: Software Service register bit definition
Address: FFB0 0010 / FFB0 0018
Timers 1 and 2 provide the CPU with programmable interval timer(s). The timers use
the F
timer provides a 27-bit programmable-down counter mechanism.
The CPU loads an initial count register (ITC) to define the timeout period. When the
current counter decrements to zero, the counter is reloaded. The reloading of the
timer can be programmed to generate an interrupt to the CPU. The CPU can read the
current count value (CTC) at any time.
These equations determine the timeout interval:
D31:00
Bits
15
31
XTALE
30
14
timing reference and an optional 9-bit prescaler or the system clock. Each
W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
TIMEOUT = [8 * (TC + 1)] / F
29
13
28
12
SWSR
Mnemonic
‘h123
27
11
and
‘h5A
26
10
‘h321
and
0
Reset
25
XTALE
9
to the register using two separate write
‘hA5
24
8
Software Service register
to the register using two separate write
SWSR
SWSR
Description
23
7
22
6
21
5
TCLK = 0; TPRE = 0
20
4
19
3
18
2
17
1
16
0