NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 195

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Non-Back-to-Back Inter-Packet-Gap register
Address: FF80 040C
Register bit assignment
Table 64: Non-Back-to-Back Inter-Packet-Gap register bit definition
D31:15
D14:08
D07
D06:00
Bits
Rsvd
15
31
30
14
N/A
R/W
N/A
R/W
Access
29
13
28
12
Reserved
IPGR1
Reserved
IPGR2
Mnemonic
IPGR1
27
11
26
10
N/A
N/A
N/A
N/A
Reset
25
9
24
8
Reserved
N/A
Non back-to-back inter-packet-gap — part 1
A programmable field that represents the optional
carrierSense window (referenced in IEEE 802.3 “Carrier
Deference”).
If carrier is found during IPGR1 timing, the MAC defers to
the carrier. If carrier is found after IPGR1 times out, the
MAC continues timing IPGR2. The transmitter causes a
collision, activating the random back off fairness algorithm
(ensuring fair access to the medium).
The range of values for IPGR1 is
The default value is
N/A
Non-back-to-back inter-packet-gap—part 2
A programmable field that represents the non-back-to-back
inter-packet-gap.
The default setting for IPGR2 is
represents these minimum IPG values:
Description
w w w . d i g i e m b e d d e d . c o m
Rsvd
In 100 Mbps: 0.96 μs
In 10 Mbps: 9.6 μs
23
7
22
6
21
5
’hC (12d)
20
4
.
IPGR2
19
’h12 (18d)
3
’h0—IPGR2
E t h e r n e t M o d u l e
18
2
, which
.
17
1
16
0
1 8 3