NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 172

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 6 0
E F E c o n f i g u r a t i o n
Table 53: Ethernet General Control register bit definition
D23
D22
D21:20
D19
D18
D17
Bits
R/W
R/W
R/W
R/W
R/W
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
ETX
ETXDMA
ETXWM
ETXREG
ETFIFOH
ETXBC
Mnemonic
0
0
0
0
0
0
Reset
Enable transmit FIFO
0
1
Set to 1 to allow data to be written to the TX FIFO.
Clear to reset the transmit side FIFO.
Enable transmit DMA
0
1
Set to 1 to allow the EFE module to issue transmit data
move requests to the DMA controller.
Clear this bit to temporarily stall transmit side Ethernet
DMA.
Do not set this bit when operating the Ethernet receiver
in interrupt service mode.
Transmit FIFO water mark before transmit start
00
01
10
11
Identifies the minimum number of bytes required in the
transmit FIFO to initiate packet transmission. A larger
watermark setting increases transmit packet latency,
allowing for more slack in the memory system FIFO fill
rate.
Note that packet transmission can also be initiated using
DMA (see "Ethernet transmitter considerations" on page
145) and the FIFO Data register (see "Ethernet FIFO Data
register" on page 167).
Enable Transmit Data register ready interrupt
Set to 1 to generate an interrupt when the TX FIFO is ready
to accept data.
Enable transmit data FIFO half empty interrupt
Must be set to 1 to generate an interrupt when the TX FIFO
is at least half empty (<256 bytes).
Enable transmit buffer complete interrupt
Set to 1 to generate an interrupt when the transmit packet
transmission is complete.
Description
Disables outbound data flow and resets the FIFO
Enables outbound data flow
Disables outbound DMA data request
Enables outbound DMA data request
25% FIFO full
50% FIFO full
75% FIFO full
Reserved