NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 178

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 6 6
E F E c o n f i g u r a t i o n
Table 55: Ethernet General Status register bit definition
Table 56 shows the relationship between the lower bits in the Ethernet General
Status register and the NS7520 pins they monitor. The significance of each bit
depends on the selected PHY and the wiring of the PHY to these pins.
D23:20
D19
D18
D17
D16
D15:10
D09:00
Bits
N/A
R
R
R/C
R
R
N/A
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Reserved
TXREGE
TXFIFOH
TXBC
TXFIFOE
RXPINS
Reserved
Mnemonic
N/A
0
0
0
1
0
N/A
Reset
N/A
Transmit register empty
Set to 1 whenever the transmit FIFO is ready to accept data.
When active high, this bit can cause an interrupt when the
ETXREGE bit is also set (in the Ethernet General Control
register).
TXREGE is never active when TXBC (D17) is set; TXBC
must be cleared to activate TXREGE.
Transmit FIFO half empty
Set to 1 when the transmit FIFO is at least half empty.
When active high, this bit can cause an interrupt when the
ETFIFOH bit is also set (in the Ethernet General Control
register).
Transmit buffer complete
Set when packet transmission is complete. When active
high, this bit can cause an interrupt when the EXTBC bit is
also set (in the Ethernet General Control register).
The TXBC bit indicates to the interrupt service routine to
read the Ethernet Transmit Status register. After the
Ethernet Transmit Status register is read, clear the TXBC
bit by writing a 1 to the TXBC bit position in this (Ethernet
General Status) register. After TXBC is cleared, the
TXREGE and TXFIFOH bits become active.
Transmit FIFO empty
Active (set to 1) when the transmit FIFO is empty.
ENDEC PHY status
The logic state of the pins RXD2, RXD1, RXD3, RXER,
and RXDV is read from this field. These pins are useful
only with an ENDEC PHY, and monitor status signals on
the PHY.
When an MII PHY is used, these bits should be ignored.
See Table 56 on page 167 for more information.
N/A
Description