NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 142

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 3 0
D M A b u f f e r d e s c r i p t o r
DMA buffer descriptor
All DMA channels operate using a buffer descriptor. Each DMA channel remains idle
until enabled using the CE bit in the DMA Control register (see "DMA Control register,"
beginning on page 136). When started, a DMA channel reads the DMA buffer
descriptor pointed to by the Buffer Descriptor Pointer register (see "Buffer Descriptor
Pointer register," beginning on page 136). When the current descriptor is completed,
the next descriptor is accessed from a circular buffer.
Each DMA buffer descriptor requires two 32-bit words for fly-by mode and three 32-
bit words stored on four-word boundaries for memory-to-memory operations.
Multiple buffer descriptors are located in 1024-byte circular buffers. The first buffer
descriptor address is provided by the DMA channel’s buffer descriptor pointer.
Subsequent buffer descriptors follow the first descriptor. The final buffer descriptor
is defined with its W (wrap) bit set. When the DMA channel encounters the W bit, the
channel wraps around to the first descriptor. If the DMA channel does not encounter a
descriptor with the W bit set, the channel wraps at the 1024-byte address boundary.
Each DMA channel can address a maximum of 128 fly-by or 64 memory-to-memory
buffer descriptors. Figure 18 and Figure 19 show each descriptor type.
Figure 18: DMA buffer descriptor — Fly-by mode
Figure 19: DMA buffer descriptor — Memory-to-memory mode
Offset + C
Offset + 0
Offset + 4
Offset + 8
Offset + 0
Offset + 4
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
31 30 29 28
W
31 30 29 28
W
I
I
L
L
Status
Status
Destination buffer pointer
Reserved
16 15
Source buffer pointer
16 15
F
F
Buffer pointer
Buffer length
Buffer length
0
0