NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 51

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIRQ and IRQ lines
Interrupt controller
Hardware Interrupts
Two wires that go into the ARM7 CPU core can interrupt the processor:
Although the interrupts are basically the same, FIRQ can interrupt IRQ.
The FIRQ line adds a simple, two-tier priority scheme to the interrupt system. Most
sources of interrupts on the ARM7TDMI come from the IRQ line. The only potential
sources for FIRQ interrupts in the ARM7TDMI come from the two built-in timers and
the watchdog timer; there is no way to generate an FIRQ signal externally. These
timers are controlled by registers in the GEN module (see "Timer Control registers,"
beginning on page 70):
Interrupts come from many different sources on the ARM7TDMI, and are managed by
the interrupt controller within the GEN module. Interrupts can be enabled or disabled
on a per-source basis using the Interrupt Enable register
a mask for the interrupt sources and ultimately controls whether an interrupt from an
ARM7TDMI module can reach the IRQ line.
There are two read-only registers in the interrupt controller:
IRQ (normal interrupt)
FIRQ (fast interrupt)
The built-in timers are controlled using the Timer Control registers
(’hFFB0 0010/18)
be set for either IRQ or FIRQ to function.
The watchdog timer is controlled using the System Control register
(’hFFB0 0000)
Interrupt Status Register Raw. Indicates the source of an ARM7TDMI
interrupt regardless of the state of the Interrupt Enable register. All
interrupts that are active in their respective module will be visible in the
Interrupt Status Register Raw.
.
. The corresponding bit in the Interrupt Enable register must
w w w . d i g i e m b e d d e d . c o m
(’hFFB0 0030)
W o r k i n g w i t h t h e C P U
, which serves as
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