NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 115

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 6: Synchronous SRAM cycles
Asynchronous SRAM cycles guarantee that the WE_ and OE_ pulses are inside the
active low pulse of CS[4:0]_. Asynchronous SRAM cycles operate a minimum of 1 wait
state at all times. Figure 7 shows asynchronous SRAM cycles.
ADDR
DATA
BCLK
CS0_
CS1_
R/W_
BEn_
WE_
OE_
TA_
All outputs change state relative to the rising edge of BCLK with the
exception of OE_ and WE_, which transition on the falling edge of BCLK.
The OE_ and WE_ signals change state on the falling edge before CS[4:0]_ is
asserted.
OE_ and WE_ remain active until the falling edge after CS[4:0]_ is
deasserted.
The rising edge of BCLK where TA_ is low defines the end of the memory
cycle (referred to as the T2 state). During synchronous read cycles, read
data is sampled on the rising edge of BCLK where TA_ is low.
T1
Sync Write
T2
T1
TW
Sync Read
T2
w w w . d i g i e m b e d d e d . c o m
T1
Sync Write
T2
M e m o r y C o n t r o l l e r M o d u l e
T1
Sync Write
T2
1 0 3