NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 165

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

E t h e r n e t M o d u l e
Interrupts are set when the DMA channel encounters buffers that are not ready. The
device driver should be designed with the smallest buffers in the A pool and the
largest buffers in the D pool. The number of available pools can be configured (from
1 to 4) using the channel enable bits in the DMA Control register (see "DMA Control
register" on page 136).
External CAM filtering
The NS7520 provides support for external CAM filtering, which requires an external
CAM controller to operate in conjunction with the MAC within the NS7520.
To support CAM filtering, the PORTC2 and PORTC5 signals must be configured for
special function signals RPSF_ and REJECT_, respectively. See "PORTC Configuration
register," beginning on page 77, for information.
The NS7520 drives the RPSF_ signal active low to identify when each Ethernet packet
starts to be transferred from the Ethernet PHY to the NS7520 internal MAC; the signal
is driven low while the fifth nibble is being transferred. The external CAM hardware
monitors the MII receive interface between the PHY and the MAC, waiting for the
RPSF_ assertion. When RPSF_ is asserted, the CAM hardware can extract the
destination address field from the MII receive bus.
After performing destination address lookup, the CAM filtering hardware can reject
the incoming packet by asserting the REJECT_ input active low during any nibble time
between RPSF_ assertion and nibble number 128.
"Ethernet cam timing" on page 291 shows the timing relationship between the RPSF_,
REJECT_, and MII receive interface signals. The MII receive interface is transferring a
packet whose first six nibbles have the values 1, 2, 3, 4, 5, and 6. The RPSF_ signal is
activated while the fifth nibble is being transferred from MII. Nibbles are transferred
in Little Endian order within a byte.
The external CAM hardware uses the RPSF_ signal to find the alignment for the
destination address. After the lookup is performed, the CAM hardware can assert the
REJECT_ signal to discard the frame. The REJECT_ signal can be asserted during any
RXCLK cycle between when RPSF_ is asserted and nibble number 128.
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