NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 228

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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SPI master transmitter
The SPI master transmitter operates as follows:
SPI master receiver
The SPI master receiver operates as follows:
Configure the character GAP timer, if you want. The character GAP timer
terminates a DMA transfer if the time between the receipt of two characters
exceeds a programmable interval. (See "Serial Channel 1, 2 Receive Character
Gap Timer," beginning on page 252, for more information.)
Configure Serial Channel Control Register B as shown:
–
–
–
–
Configure Serial Channel Control Register A as shown:
–
–
Changes its TXD output on the falling edge of the SPI clock signal while the
SPI enable signal is driven active low. The SPI slave devices should sample
data in the rising edge of the SPI clock signal.
Drives the SPI enable signal active low from the falling edge of the SPI clock
for the first bit of a byte being transmitted, and inactive high after the
rising edge of the SPI clock signal during the eighth bit of the byte currently
transmitted.
Drives the SPI enable signal active low to identify when data is being
transmitted. The SPI clock signal never transitions from low to high while
the internal SPI enable signal is inactive high.
Transmits bytes when data is available in the TX FIFO. When the TX FIFO
becomes empty, the SPI enable signal is driven inactive high until more data
is available in the TX FIFO.
Samples the RXD input on the rising edge of the SPI clock signal while the
SPI enable signal is driven active low.
RBGT: 1 to enable the buffer GAP timer
RCGT: 1 to enable the character GAP timer
MODE: 10 for master mode
BITORDR: user-defined
CE: 1 for enable
WLS: 11 for 8-bit operation
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