NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 194

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NS7520B-1-I46

Manufacturer Part Number
NS7520B-1-I46
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Datasheets

Specifications of NS7520B-1-I46

Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Price
Part Number:
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Back-to-Back Inter-Packet-Gap register
1 8 2
E F E c o n f i g u r a t i o n
Address: FF80 0408
Register bit assignment
Table 63: Back-to-Back Inter-Packet-Gap register bit definition
D31:07
D06:00
Bits
15
31
30
14
N/A
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
29
13
28
12
Reserved
IPGT
Mnemonic
Reserved
27
11
26
10
N/A
N/A
Reset
25
9
24
8
Reserved
N/A
Back-to-back inter-packet-gap
A programmable field that represents the nibble time offset
of the minimum possible period between the end of any
transmitted packet to the beginning of the next packet.
Description
proper period in nibble times minus 3.
The recommended setting is
represents these minimum IPG values:
— In 100 Mbps: 0.96 μs
— In 10 Mbps: 9.6 μs
proper period in nibble times minus 6.
The recommended setting is
represents these minimum IPG values:
— In 100 Mbps: 0.96 μs
— In 10 Mbps: 9.6 μs
Full-duplex mode. The register value should be the
Half-duplex mode. The register value should be the
23
7
22
6
21
5
20
4
IPGT
19
3
’h15 (21d)
’h12 (18d)
18
2
, which
, which
17
1
16
0

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