NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 177

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 55: Ethernet General Status register bit definition
D29:28
D27
D26
D25
D24
Bits
R
R
R
R/C
R/W
Access
RXFDB
RXREGR
RXFIFOH
RXBR
RXSKIP
Mnemonic
0
0
0
0
0
Reset
Receive FIFO data available
Valid only when RXREGR (D27) = 1.
00
01
10
11
Must be used in conjunction with RXREGR. When
RXREGR is set to 1, RXFDB identifies how many bytes
are available in the Receive Data register.
Receive register ready
Set to 1 when data is available to be read from the FIFO
Data register. When set active high, this bit can cause an
interrupt when the ERXREG bit is also set (in the Ethernet
General Control register).
RXREGR is never active when RXBR (D25) is set; RXBR
must be cleared to activate RXREGR.
Receive FIFO half full
Set to 1 when the receive FIFO is at least half full (>1024
bytes). When set active high, this bit can cause an interrupt
when the ERFIFOH bit is set (in the Ethernet General
Control register).
Receive buffer ready
Set to 1 when a new packet is available in the receive FIFO.
When set active high, this bit can cause an interrupt when
the ERXBR bit is also set (in the Ethernet General Control
register).
RXBR indicates to the interrupt service routine (ISR) that
the Receive Status register should be read. After reading
that register, clear RXBR by writing a 1 to the RXBR
position in this (Ethernet General Status) register. When
RXBR is cleared, RXREGR and RXFIFOH become active.
Receive buffer skip
Used (written) instead of clearing the RXBR bit. Writing to
RXSKIP clears the RXBR bit and flushes the next available
packet from the receive FIFO.
Using RXSKIP is a means of performing receive packet
filtering in the interrupt service routine; the packet simply
is flushed from the FIFO rather than read out of the FIFO.
Description
w w w . d i g i e m b e d d e d . c o m
Full-word
One byte
Half-word
Three bytes; LENDIAN determines which three
E t h e r n e t M o d u l e
1 6 5