NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 122

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Single cycle read/write
1 1 0
F P / E D O D R A M c o n t r o l l e r
Figure 9 shows FP DRAM normal read and write cycles.
Figure 9: Normal FP DRAM bus cycles
All DRAM cycles must operate a minimum of 1 wait state. (If the controller is
programmed for 0 wait states, operation is unpredictable). A single wait state DRAM
cycle requires the DRAM devices to tolerate a single BCLK cycle for RAS precharge
and CAS access timing.
Important:
DADDR
ADDR
BCLK
RAS_
CAS_
DATA
R/W_
WE_
OE_
TA_
Normal and burst (FP/EDO) cycles
Programmable wait states for normal (also first cycle ion burst access) and
burst cycles
Programmable base address and chip select size
The CAS_ signal is deasserted on the rising edge in which TA_ is recognized.
The RAS_ signal is deasserted on the falling edge of BCLK after CAS_ is
asserted.
T1
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
You cannot set the PS field to
TW
TW
FP DRAM Write
T2
T1
2’b11
TW
for FP DRAM.
TW
FP DRAM Read
T2
T1
TW