NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 31

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 6: Ethernet interface MAC pinout
Signal descriptions
The Ethernet MII (media independent interface) provides the connection between the
Ethernet PHY and the MAC (media access controller).
Table 7: Ethernet interface MAC signal description
RXD2
RXD1
RXD0
RXER
RXDV
MDC
MDIO
TXCLK
TXD3
TXD2
TXD1
TXD0
TXER
TXEN
Symbol
Mnemonic
GP input
GP input
RXD
GP input
GP input
Transmit clock
Transmit enable
MII management clock
Management data IO
Transmit data signals
Transmit coding error
Signal
B15
A15
B13
C15
D15
Pin
I
I
I
I
I
I/O
Provides the clock for the MDIO serial data channel. The
MDC signal is an NS7520 output. The frequency is derived
from the system operating frequency per the CLKS field
setting (see the CLKS field in Table 69: "MII Management
Configuration register bit definition" on page 189).
A bi-directional signal that provides a serial data channel
between the NS7520 and the external Ethernet PHY
module.
An input to the NS7520 from the external PHY module.
TXCLK provides the synchronous data clock for transmit
data.
Nibble bus used by the NS7520 to drive data to the external
Ethernet PHY. All transmit data signals are synchronized
to TXCLK.
In ENDEC mode, only TXD0 is used for transmit data.
Output asserted by the NS7520 when an error has occurred
in the transmit data stream.
Asserted when the NS7520 drives valid data on the TXD
outputs. This signal is synchronized to TXCLK.
Description
OD
w w w . d i g i e m b e d d e d . c o m
RX data 2
RX data 1
RX data 0
RX error
RX data valid
Description
P i n o u t a n d P a c k a g i n g
Receive data
Read state in bit 11
Read state in bit 10
Read state in bit 15
Read state in bit 13
1 9