W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 63

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

power source. If there is no 5VSB power, the power source is VBAT. This is designed to save power
consumption of the battery.
When the case is closed, CASEOPEN# (Pin 76) must be pulled high by an external 2M Ω resistor that
is connected to VBAT (Pin 74). When the case is opened, CASEOPEN# will be switched from high to
low. Meanwhile, the detection circuit inside the IC latches the signal. As a result, the interrupt status
and the real-time status can be read at the registers next time when the computer is powered. The
status will not be cleared unless Bank 0, Index 46h, bit 7, or CR[E6h] bit 5 at Logical Device A is set to
“1” first and this bit is self-cleared to “0”.
The W83627UHG provides an alarm output function at the BEEP/GP21 pin. The BEEP/GP21 pin is a
multi-function pin and can be configured as BEEP output, if Logical Device B, CR[F2h], bit 1 is set to
zero.
The BEEP outputs a warning tone when one of the monitored parameters in the following events is out
of the preset range.
The BEEP alarm function is enabled or disabled by the control bit at Hardware Monitor Device, Bank 0,
Index 57h, bit 7. Also, each event has their individual enable bit at Hardware Monitor Device, Bank 0,
Index 56h bit[7:0], Index 57h bit[6:0] and Bank 4, Index 53h, bit[1:0].
CASEOPEN#
CASEOPEN#
7.7.4 BEEP Alarm Function
CASEOPEN
CASEOPEN
CASEOPEN
CASEOPEN
Any voltage input of the eight pins (CPUVCORE, VIN[0..2], 5VCC, AVCC , 5VSB and VBAT) is
out of the allowed range;
Any temperature input of the three pins (SYSTIN and CPUTIN) exceeds the limit;
Any fan input of the two pins (SYSFANIN and CPUFANIN) exceeds the limit;
CASEOPEN# input pin is sampled low;
User-defined bit (Bank 4, Index 53h, bit 5) is written to 1.
STATUS
STATUS
CLEAR
CLEAR
Figure 7-22 Caseopen Mechanism
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Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44