W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 18

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.1
5.2
LFRAME#
DRVDEN0
LRESET#
SYMBOL
SYMBOL
LAD[3:0]
SERIRQ
PCICLK
INDEX#
LDRQ#
DSRF#
CLKIN
CTSF#
RTSF#
PME#
MOA#
DSA#
GP64
LPC Interface
FDC Interface
PIN
PIN
24-
19
86
21
22
23
27
29
30
5
6
7
8
I/OD
OD
OD
OD
I/O
I/O
IN
O
I/O
OD
IN
O
IN
IN
IN
IN
I/O
IN
tsu
24
12p3
12tp3
12tp3
24
t
12ts
24
t
24
tsp3
tsp3
tsp3
t
12
Drive Density Select bit 0.
Clear To Send. It is the modem control input. The function of
these pins can be tested by reading bit 4 of the handshake
status register.
General purpose I/O port 6 bit 4.
Motor A On. When set to 0, this pin enables disk drive A. This is
an open-drain output.
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open-drain output.
UART F Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
This Schmitt-trigger input from the disk drive is active-low when
the head is positioned over the beginning of a track marked by
an index hole. This input pin needs to connect a pulled-up 1-
KΩ resistor to 5V for Floppy Drive compatibility.
System clock input, either 24MHz or 48MHz. The actual
frequency must be specified in register. The default value is
48MHz.
Generated PME event.
PCI-clock 33-MHz input.
Encoded DMA Request signal.
Serialized IRQ input / output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates the start of a new cycle or the termination of a broken
cycle.
Reset signal. It can be connected to the PCIRST# signal on the
host.
-3-
DESCRIPTION
DESCRIPTION
Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44