W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 100

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9. FLOPPY DISK CONTROLLER
The floppy disk controller (FDC) of the W83627UHG integrates all of the logic required for floppy disk
control. The FDC implements a FIFO, which provides better system performance in multi-master
systems, and the digital data separator supports data rates up to 2 M bits/sec.
The FDC includes the following blocks: Precompensation, Data Rate Selection, Digital Data Separator,
FIFO, and FDC Core. The rest of this section discusses these blocks through the following topics:
FIFO, Data Separator, Write Precompensation, Perpendicular Recording mode, FDC core, FDC
commands, and FDC registers.
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM
(Request for Master) and DIO (Data Input/Output) bits in the Main Status Register.
The FIFO is defaulted to disabled mode after any form of reset, which maintains PC/AT hardware
compatibility. The default values can be changed through the configure command. The advantage of
the FIFO is that it allows a larger DMA latency in the system without causing disk errors. The following
tables give several examples of the delays with the FIFO. The data are based upon the following
formula:
9.1
9.1.1 FIFO (Data)
FIFO THRESHOLD
FIFO THRESHOLD
FDC Functional Description
15 Byte
15 Byte
2 Byte
8 Byte
1 Byte
2 Byte
8 Byte
1 Byte
DELAY = THRESHOLD # × (1 / DATA RATE) * 8 - 1.5 μ s
Table 9-1 The Delays of the FIFO
Data Rate
Data Rate
2 × 16 μ s - 1.5 μ s = 30.5 μ s
8 × 16 μ s - 1.5 μ s = 6.5 μ s
15 × 16 μ s - 1.5 μ s = 238.5 μ s
1 × 8 μ s - 1.5 μ s = 6.5 μ s
2 × 8 μ s - 1.5 μ s = 14.5 μ s
8 × 8 μ s - 1.5 μ s = 62.5 μ s
15 × 8 μ s - 1.5 μ s = 118.5 μ s
1 × 16 μ s - 1.5 μ s = 14.5 μ s
MAXIMUM DELAY UNTIL SERVICING AT 500K BPS
MAXIMUM DELAY UNTIL SERVICING AT 1M BPS
-85-
Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44