W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 190

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR E6h. (Default 1Ch)
CR E7h. (Default 00h)
2~1
BIT READ / WRITE
BIT
1-0
7
6
5
4
3
0
5
4
3
2
Reserved.
R / W-Clear
Reserved.
READ / WRITE
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
ENMDAT => (VSB)
3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1])
define the combinations of the mouse wake-up events. Please refer to the
table in CRE0[4] for the details.
CASEOPEN Clear Control. (VSB)
Write 1 to this bit will clear CASEOPEN status. This bit will clear the status
itself. The function is the same as Index 46h bit 7 of H/W Monitor part.
Power-loss Last State Flag. (VBAT)
0: ON
1: OFF.
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
0: 300 ~ 500 ms.
1: 200 ~ 300 ms.
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
00: No delay time.
10: 96 ms
PWROK_TRIG =>
Write 1 to re-trigger the PWROK signal from low to high.
GPIO 4 reset source control bit.
=0 Enable GPIO 4 reset source by LRESET#
=1 Disable GPIO 4 reset source by LRESET#
GPIO 3 reset source control bit.
=0 Enable GPIO 3 reset source by LRESET#
=1 Disable GPIO 3 reset source by LRESET#
GPIO 2 reset source control bit.
=0 Enable GPIO 2 reset source by LRESET#
=1 Disable GPIO 2 reset source by LRESET#
GP25~27 reset source control bit.
=0 LRESET#
=1 RSMRST#
-175-
DESCRIPTION
DESCRIPTION
01: Delay 32 ms
11: Delay 250 ms
Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44