W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 141

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.12.1.
The software must handle P1284 negotiation and all operations prior to a data transfer in SPP or PS/2
modes (000 or 001). The hardware provides an automatic control line handshake, moving data
between the FIFO and the ECP port, only in the data transfer phase (mode 011 or 010).
If the port is in mode 000 or 001, it may switch to any other mode. If the port is not in mode 000 or 001,
it can only be switched into mode 000 or 001. The direction can only be changed in mode 001.
In extended forward mode, the software should wait for the FIFO to be empty before switching back to
mode 000 or 001. In ECP reverse mode, the software should wait for all the data to be read from the
FIFO before changing back to mode 000 or 001.
11.3.12.2.
ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal
data are transferred when HostAck is high, and an 8-bit command is transferred when HostAck is low.
The most significant bits of the command indicate whether it is a run-length count (for compression) or
a channel address.
In the reverse direction, normal data are transferred when PeriphAck is high, and an 8-bit command is
transferred when PeriphAck is low. The most significant bit of the command is always zero.
11.3.12.3.
The W83627UHG hardware supports RLE decompression and can transfer compressed data to a
peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer
data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to
ecpDFifo.
11.3.12.4.
The FIFO threshold is set in CR5. All data transferred to or from the parallel port can proceed in DMA
or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used in Parallel
Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.
DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. DMA uses the standard PC DMA
services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA
empties or fills the FIFO using the appropriate direction and mode. When the terminal count in the
DMA controller is reached, an interrupt is generated, and serviceIntr is asserted, which will disable the
DMA.
The ECP and parallel port FIFOs can also be operated using interrupt-driven, programmed I/O.
Programmed I/O transfers are
11.3.13 DMA Transfers
11.3.14 Programmed I/O (NON-DMA) Mode
1. To the ecpDFifo at 400H and ecpAFifo at 000H
Mode Switching
Command/Data
Data Compression
FIFO Operation
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Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44