W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 62

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The SMI#/OVT# pin is a multi-function pin. It can be in SMI# mode or in OVT# mode by setting
Configuration Register CR[29h], bit 6 to one or zero, respectively. In OVT# mode, it can monitor
temperatures, and it is enabled or disabled for SYSTIN and CPUTIN by Bank0 Index 18h, bit 6; and
Bank0, Index 4Ch, bit 3.
The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this
figure.
If Bank0, Index 18h, bit 4, and Bank1 Index 52h, bit1 are set to zero, the OVT# pin is in comparator
mode. In comparator mode, the OVT# pin can create an interrupt once the current temperature
exceeds T
asserted once the temperature has exceeded T
If Bank0, Index 18h, bit 4, and Bank1 Index 52h, bit1 are set to one, the OVT# pin is in interrupt mode.
In interrupt mode, the OVT# pin can create an interrupt once the current temperature rises above T
or when the temperature falls below T
generates an interrupt, this mode does not generate additional interrupts, even if the temperature
remains above T
the interrupt status registers. The OVT# pin is asserted when an interrupt is generated and remains
asserted until the interrupt is reset.
The purpose of Caseopen function is used to detect whether the computer case has been opened and
possibly tampered with. This feature must function even when there is no 5VSB power. Consequently,
the power source for the circuit is from either Pin 74 (VBAT) or Pin 61 (5VSB). 5VSB is the default
7.7.2 OVT# Interrupt Mode
7.7.3 Caseopen Detection
reset by reading all the interrupt status registers, or subsequent events do not generate interrupts.
This is illustrated in the figure above.
O
and continues to create interrupts until the temperature falls below T
(Comparator Mode; default)
O
, until the temperature falls below T
(Interrupt Mode)
Figure 7-21 OVT# Modes of Temperature Inputs
T
HYST
OVT#
OVT#
To
*Interrupt Reset when Temperature sensor registers are read
HYST
. Once the temperature rises above T
O
*
and has not yet fallen below T
-47-
HYST
. This interrupt must be reset by reading all
*
Publication Release Date: March 24, 2008
W83627UHG
HYST
*
HYST
.
. The OVT# pin is
O
, however, and
Revision 1.44
O