W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 23
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W83627UHG
Manufacturer Part Number
W83627UHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Specifications of W83627UHG
Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V, 5V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PFDCUART
FAN_SET
SYMBOL
HEFRAS
RTSB#
RTSC#
RTSD#
RTSE#
DTRA#
DTRB#
DTRC#
DTRD#
RTSF
DSA#
GP15
GP35
GP45
GP55
GP14
GP34
GP44
PIN
111
119
127
112
120
80
52
81
8
I/OD
I/OD
I/OD
I/OD
I/OD
I/OD
I/OD
OD
IN
IN
IN
O
O
I/O
O
O
O
O
O
O
O
12
24
cd
cd
cd
8
8
8
8
8
8
8
24
12t
12t
12t
8t
8
8
8
During power-on reset, this pin is pulled down internally and is
defined as HEFRAS, which provides the power-on value for
CR26 bit 6 (HEFRAS). The PCB layout should reserve space for
a 1-kΩ resistor to pull down this pin so as to ensure the selection
of I/O port’s configuration address to 2EH, and a 1-kΩ resistor is
recommended to pull it up if 4EH is selected as I/O port′s
configuration address.
UART B Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
General-purpose I/O port 1 bit 5.
UART C Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
General-purpose I/O port 3 bit 5.
UART D Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
Determines the initial FAN speed. Power-on configuration for 2
fan speeds, 50% or 100%. During power-on reset, this pin needs
a pulled-up or a pull-down resistor to decide whether the fan
speed is 50% or 100%.
General-purpose I/O port 4 bit 5.
UART E Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
General-purpose I/O port 5 bit 5.
UART F Request To Send. An active-low signal informs the
modem or data set that the controller is ready to send data.
Drive Select A. When set to 0, this pin enables disk drive A. This
is an open drain output.
UART A Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
During power-on reset, this pin is pulled down internally and is
defined as FDC enable, which provides the power-on value for
CR24 bit 1. A 1 kΩ is reserved to pull down and a 1 kΩ resistor
is recommended if intends to pull-up to enable UART F.
UART B Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
General-purpose I/O port 1 bit 4.
UART C Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
General-purpose I/O port 3 bit 4.
UART D Data Terminal Ready. An active-low signal informs the
modem or data set that the controller is ready to communicate.
General-purpose I/O port 4 bit 4.
-8-
DESCRIPTION
Publication Release Date: March 24, 2008
W83627UHG
Revision 1.44
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