W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 156

• Manufacturer Part Number: W83627UHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627UHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V, 5V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14. SERIALIZED IRQ
The W83627UHG supports a serialized IRQ scheme. This allows a signal line to be used to report the
parallel interrupt requests. Since more than one device may need to share the signal serial SERIRQ
signal, an open drain signal scheme is employed. The clock source is the PCI clock. The serialized
interrupt is transferred on the SERIRQ signal, one cycle consisting of three frames types: the Start
Frame, the IRQ/Data Frame, and the Stop Frame.
There are two modes of operation for the SERIRQ Start Frame: the Quiet mode and the Continuous
mode.
In the Quiet mode, the W83627UHG drives the SERIRQ signal active low for one clock, and then tri-
states it. This brings all the state machines of the W83627UHG from idle to active states. The host
controller (the South Bridge) then takes over driving SERIRQ signal low in the next clock and
continues driving the SERIRQ low for programmable 3 to 7 clock periods. This makes the total number
of clocks low 4 to 8 clock periods. After these clocks, the host controller drives the SERIRQ high for
one clock and then tri-states it.
In the Continuous mode, the START Frame can only be initiated by the host controller to update the
information of the IRQ/Data Frame. The host controller drives the SERIRQ signal low for 4 to 8 clock
periods. Upon a reset, the SERIRQ signal is defaulted to the Continuous mode for the host controller
to initiate the first Start Frame.
Please see the diagram below for more details.
PCICLK
SER IRQ
Drive Source
H=Host Control
Note:
1. The Start Frame pulse can be 4-8 clocks wide.
2. The first clock of Start Frame is driven low by the W83627UHG because IRQ1 of the W83627UHG
14.1 Start Frame
Figure 14-1 Start Frame Timing with Source Sampled A Low Pulse on IRQ1
IRQ1
SL
or
H
2
SL=Slave Control
START
Host Controller
START FRAME
H
1
R
T
IRQ0 FRAME
-141-
S
None
R=Recovery
R
T
Publication Release Date: March 24, 2008
IRQ1 FRAME
S
IRQ1
T=Turn-around
R
T
W83627UHG
SMI# FRAME
S
None
R
Revision 1.44
T
S=Sample