W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 128

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W83627UHG

Manufacturer Part Number
W83627UHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheets

Specifications of W83627UHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V, 5V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
This 8-bit register enables and disables the five types of controller interrupts separately. A selected
interrupt can be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally
disabled by setting bits 0 through 3 to logical 0.
DEFAULT
0
10.2.7 Interrupt Control Register (ICR) (Read/Write)
BIT
NAME
7
6
5
4
3
2
1
0
BIT
0
ISR
0
0
0
0
EHSRI (Handshake Status Interrupt Enable). Set this bit to logical 1 to enable the
handshake status register interrupt.
EUSRI (UART Receive Status Interrupt Enable). Set this bit to logical 1 to enable the
UART status register interrupt.
ETBREI (TBR Empty Interrupt Enable). Set this bit to logical 1 to enable the TBR empty
interrupt.
ERDRI (RBR Data Ready Interrupt Enable). Set this bit to logical 1 to enable the RBR
data ready interrupt.
0
0
7
0
Fourth
6
0
Handshake status
5
0
INTERRUPT SET AND FUNCTION
DESCRIPTION
-113-
1. TCTS = 1
3. FERI = 1
4
0
EHSRI
4. TDCD = 1
2. TDSR = 1
3
0
Publication Release Date: March 24, 2008
EUSRI
2
0
W83627UHG
Read HSR
ETBREI
1
0
Revision 1.44
ERDRI
0
0

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